//
//  user.v
//
//  Generische Slave-Mode Anwendung: Realisiert ein les-/schreibbares
//  Hardware-Register
//

module user(
	    CLK,
	    RESET,  
	    ADDRESSED,
	    WRITE,
	    DATAIN,
	    DATAOUT,
	    ADDRESS,
	    IRQ
	    );

   // Eingaenge
   input           CLK;
   input           RESET;
   input           ADDRESSED;
   input           WRITE;
   input [31:0]    DATAIN;
   input [23:2]    ADDRESS;

   // Ausgaenge
   output [31:0]   DATAOUT;
   output          IRQ;

   wire 	   IRQ = 1'b0; // wird im Slave-Mode nicht gebraucht

	 reg [15:0] result;
   reg [7:0] 	   dividend, divisor, tempDividend;
   wire [7:0] 	   quot, remd;

   PipelinedDivider pd
   (
	 	.dividend(dividend),
		.divisor(divisor),
		.quot(quot),
		.remd(remd),
		.clk(CLK),
		.rfd()
   );

		
   localparam REMD = 3'b001; //0x10000004
   localparam QUOT = 3'b010; //0x10000008
	 localparam DIVIDEND = 3'b011; //0x1000000C
	 localparam DIVISOR = 3'b000; // 0x10000000
	 localparam READ_RESULT = 3'b100; //0x10000010
   
   // Beginn der Anwendung **************************************************

   // Ausgabedaten auf Bus legen
   assign DATAOUT = (ADDRESS[4:2] ==  READ_RESULT) ? result :
												(ADDRESS[4:2] ==  QUOT) ? quot :
														(ADDRESS[4:2] ==  REMD) ? remd :		    										
																32'hC0FEEE11;

   // Steuerung
   always @(posedge CLK or posedge RESET) begin
      // Initialisiere Register
      if (RESET) begin
	 			dividend  <= 32'hDEADBEEF;
	 			divisor  <= 32'hDEADBEEF;
	 // Schreibzugriff auf RC
      end 
			else if (ADDRESSED & WRITE) begin
				if(ADDRESS[4:2] == DIVIDEND) begin
					tempDividend <= DATAIN;		
				end			
				else if(ADDRESS[4:2] == DIVISOR) begin
					dividend <= tempDividend;
					divisor <= DATAIN;
				end
			end
   end

// result berechnen
   always @(remd or quot) begin
      result[15:8] = quot;
			result[7:0] = remd;
   end

endmodule
